Conventionally, a wide range of development has been made in the field of the lighting devices and the display devices which use light emitting elements (which may also be called semiconductor light emitting elements) as a light source. In a known light emitting device, a wiring pattern is formed on a substrate, and a light emitting chip mounted on the substrate is connected to the wiring pattern by die-bonding. Further in this light emitting device, an alignment mark is formed on the substrate in order to position the substrate in the step of die-bonding the lighting emitting chip or in other steps.
In a conventional process, the alignment mark is plated simultaneously with the wiring pattern. However, since an alignment mark has a small area, when such an alignment mark is formed by plating, the current density in the alignment mark forming site increases during the plating and causes uneven plating in the plated layer. Disadvantageously, uneven plating hampers clear recognition of the alignment mark.
To reduce the defects due to uneven plating, Patent Literature 1 discloses integral formation of an alignment mark and a wiring pattern, and formation of a large-area alignment mark.
Additionally, for a small-area alignment mark, it is preferable to increase its adhesion property to the substrate in order to prevent its detachment from the substrate. For this purpose, Patent Literatures 2 and 3 employ the metal wiring and the insulated substrate which both contain glass components and thereby improve the adhesion property therebetween.